{"product_id":"yx-os24-usrp-b210-wideband-sdr-signal-processing-platform-with-ad9361-and-k325t-fpga-uhd-compatible-for-openwifi-development","title":"YX-OS24 USRP B210 Wideband SDR Signal Processing Platform with AD9361 and K325T FPGA, UHD Compatible for OpenWiFi Development","description":"\u003ch1\u003eUSRP B210 Upgrade SDR Platform\u003cbr\u003e\u003cimg src=\"https:\/\/cdn.shopify.com\/s\/files\/1\/0733\/7367\/9781\/files\/ScreenShot_2026-01-31_205023_735.png?v=1769865740\" alt=\"\"\u003e\u003cbr\u003e\n\u003c\/h1\u003e\n\u003cp\u003e\u003cbr\u003e\u003c\/p\u003e\n\u003cdiv class=\"card\"\u003e\n\u003ch2\u003eProduct Overview\u003c\/h2\u003e\n\u003cp\u003eThe\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003eDRF UHD B210 upgraded SDR platform\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003efeatures a frequency range from\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003e70 MHz to 6 GHz\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eand is fully compatible with the official UHD driver. It supports\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003eGNU Radio\u003c\/strong\u003e,\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003eC++ \/ Python API\u003c\/strong\u003e,\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003eMATLAB\u003c\/strong\u003e, and\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003eVivado-based FPGA development\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003e(not legacy ISE). Wireless operation is\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003eintended for learning and research only\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eand must comply with local regulations.\u003c\/p\u003e\n\u003c\/div\u003e\n\u003cdiv class=\"card\"\u003e\n\u003ch2\u003eCore Hardware Specifications\u003c\/h2\u003e\n\u003ctable\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003cth\u003eParameter\u003c\/th\u003e\n\u003cth\u003eSpecification\u003c\/th\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eRF Frequency Range\u003c\/td\u003e\n\u003ctd\u003e70 MHz – 6 GHz\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eRF Transceiver\u003c\/td\u003e\n\u003ctd\u003eAnalog Devices AD9361\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eMain Processor\u003c\/td\u003e\n\u003ctd\u003eXilinx XC7K325T\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eADC \/ DAC Resolution\u003c\/td\u003e\n\u003ctd\u003e12-bit, variable sampling rate\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eRF Channels\u003c\/td\u003e\n\u003ctd\u003e2 TX \/ 2 RX\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eOperating Modes\u003c\/td\u003e\n\u003ctd\u003eHalf-duplex \/ Full-duplex\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eMIMO Support\u003c\/td\u003e\n\u003ctd\u003e2×2 MIMO\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eMax Bandwidth (1×1 Mode)\u003c\/td\u003e\n\u003ctd\u003e56 MHz\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eGPIO\u003c\/td\u003e\n\u003ctd\u003e8 external GPIO pins\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\n\u003c\/div\u003e\n\u003cdiv class=\"card\"\u003e\n\u003ch2\u003eInterfaces \u0026amp; Synchronization\u003c\/h2\u003e\n\u003ctable\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003cth\u003eInterface\u003c\/th\u003e\n\u003cth\u003eDescription\u003c\/th\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eUSB Interface\u003c\/td\u003e\n\u003ctd\u003eUSB 3.0 with Type-C connector\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eGPS\u003c\/td\u003e\n\u003ctd\u003eIntegrated GPS synchronization\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eReference Clock\u003c\/td\u003e\n\u003ctd\u003eExternal 10 MHz reference input supported\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePPS\u003c\/td\u003e\n\u003ctd\u003eExternal 1PPS synchronization input supported\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\n\u003c\/div\u003e\n\u003cdiv class=\"card\"\u003e\n\u003ch2\u003eSoftware \u0026amp; Development Support\u003c\/h2\u003e\n\u003cul\u003e\n\u003cli\u003eFully compatible with UHD driver\u003c\/li\u003e\n\u003cli\u003eSupports GNU Radio development\u003c\/li\u003e\n\u003cli\u003eSupports C++ and Python API\u003c\/li\u003e\n\u003cli\u003eSupports MATLAB-based SDR development\u003c\/li\u003e\n\u003cli\u003eFPGA development using Vivado (non-legacy ISE)\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003c\/div\u003e\n\u003cdiv class=\"card\"\u003e\u003cbr\u003e\u003c\/div\u003e\n\u003cdiv class=\"card\"\u003e\n\u003ch2\u003eUsage Disclaimer\u003c\/h2\u003e\n\u003cp\u003eThis SDR platform is intended for\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003elearning, research, and experimental use only\u003c\/strong\u003e. All wireless operations must comply with local laws and regulations. Any illegal use is strictly prohibited.\u003c\/p\u003e\n\u003c\/div\u003e","brand":"YanTechLab","offers":[{"title":"XC7K325T + AD9361","offer_id":47801992806565,"sku":null,"price":432.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0733\/7367\/9781\/files\/IMG_0207.jpg?v=1769863399","url":"https:\/\/yantechlab.com\/de\/products\/yx-os24-usrp-b210-wideband-sdr-signal-processing-platform-with-ad9361-and-k325t-fpga-uhd-compatible-for-openwifi-development","provider":"YanTechLab","version":"1.0","type":"link"}