5G Small Cell Development in Practice

Dual RX/TX RF Board Based on XC7Z100 + ADRV9009 (Full Workflow)

In 5G infrastructure deployment, small cells serve as a critical extension to macro base stations, solving indoor coverage and high-density capacity challenges. The RF board is the core component that directly determines system-level performance.

This article provides a complete end-to-end implementation guide — from hardware design to driver configuration and performance optimization — based entirely on a dual-channel RF architecture using XC7Z100 and ADRV9009.

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1. Hardware Architecture Design & Key Component Selection

1.1 System Architecture

This RF board follows a classic FPGA + RF Frontend architecture:

• Processing Unit: XC7Z100 SoC (PS: Dual Cortex-A9, PL: FPGA Fabric)
• RF Transceiver: ADRV9009 Dual-Channel Transceiver
• Interfaces & Storage: DDR3, QSPI Flash, Gigabit Ethernet

Advantages:

• High Performance Processing: ARM handles protocol stack, FPGA accelerates PHY layer
• Programmable Flexibility: PL supports reconfigurable logic
• High Integration: ADRV9009 integrates dual RX/TX

1.2 Core Component Comparison

Component	XC7Z100-2FFG900I	ADRV9009BBCZ
Architecture	Dual Cortex-A9 + Artix-7 FPGA	Dual RF Transceiver
Processing	866MHz ARM + 125MHz FPGA	122.88 MS/s ADC/DAC
RF Range	N/A	100MHz - 6GHz
Power	4W (Typ)	1.8W / Channel (RX)
Interface	USB / Ethernet / FMC	JESD204B/C

Note: The PL side must connect to ADRV9009 via FMC with JESD204B support.

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2. Hardware Connection & Signal Integrity Design

2.1 Interface Design

ADRV9009 communicates with XC7Z100 through:

1. JESD204B Interface (4 lanes @ 6.144Gbps)
   • High-speed ADC/DAC data transfer
   • Trace skew must be within ±50ps
2. SPI Interface
   • Register configuration
   • Isolation buffer recommended
3. Clock Network
   • Reference clock: 122.88MHz ±1ppm
   • SYSREF for deterministic latency

set_property CONFIG.LANES 4 [get_ips jesd204_0]
set_property CONFIG.C_NUM_LINKS 1 [get_ips jesd204_0]
set_property CONFIG.C_LANE_RATE 6.144 [get_ips jesd204_0]

2.2 PCB Design

• 8-layer stackup recommended
• 50Ω single-ended / 100Ω differential
• ADRV9009 requires 6 independent power rails

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3. Software Environment & Driver Configuration

3.1 Toolchain Setup

• Vivado 2020.1
• PetaLinux 2020.1
• ADI IIO Linux Drivers

git clone https://github.com/analogdevicesinc/linux.git
cd linux
make ARCH=arm xilinx_zynq_defconfig
make ARCH=arm menuconfig

3.2 Device Tree Configuration

adrv9009: adrv9009@0 {
    compatible = "adi,adrv9009";
    reg = <0>;
    spi-max-frequency = <25000000>;
};

3.3 RF Initialization Flow

1. Load firmware via SPI
2. Configure JESD204B link
3. Set RF frequency & bandwidth
4. Calibration (DCXO, QEC, LO leakage)
5. Enable data path

Temperature variation beyond ±5°C requires recalibration.

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4. Debugging & Performance Optimization

4.1 Troubleshooting

Issue	Cause	Solution
JESD Loss	Clock mismatch	Check SYSREF
Poor EVM	LO leakage	Run calibration
Low Sensitivity	Gain config	Adjust gain table
Packet Loss	DMA error	Check AXI flow

4.2 Performance Results

• TX Power: 17 dBm
• EVM: 0.6%
• ACLR: -65 dBc
• Sensitivity: -92 dBm

4.3 Low Latency Optimization

1. AXI Stream direct connection
2. Scatter-Gather DMA
3. PL DDR buffering

struct dma_slave_config config = {
    .direction = DMA_DEV_TO_MEM,
    .src_addr_width = DMA_SLAVE_BUSWIDTH_8_BYTES,
    .dst_maxburst = 16,
};

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5. Rapid Project Deployment

To accelerate development, you can start directly with a ready-to-use platform including schematics and firmware:

XC7Z100 + ADRV9009 SDR RF Board