Understanding the ADRV9009 Receive Chain Digital Filters

A detailed walkthrough of the ADRV9009 receive signal chain—from quadrature mixing to programmable FIR filters. 100MHz bandwidth case study with filter coefficient analysis.

The ADRV9009 receive chain consists of the following stages in signal flow order: quadrature mixing (modulation/demodulation), TIA (transimpedance amplifier), ADC, first decimation stage, second decimation stage, programmable FIR filter (with decimation option), quadrature correction, DC correction, DC gain, and IF translation.

Quadrature Mixing (Demodulation)

Each channel contains two mixers and a quadrature local oscillator (LO) signal. In the ADRV9009, RX1/2 and TX1/2 share a common LO generator, which limits operation to TDD mode—FDD mode is not supported. The LO signal is synthesized by the internal PLL using an external reference clock. LO phase noise directly impacts transmit modulation EVM and receiver performance, making external reference clock quality (phase noise, stability) critical in hardware design.

Key observation: After zero-IF quadrature demodulation, the baseband bandwidth of the I/Q branches is only half that of the real signal.

100MHz Signal Bandwidth Case Study (Sampling Rate: 1966.08 MHz)

This analysis uses a configuration targeting 100MHz real signal bandwidth. The ADC sampling rate is 1966.08 MHz, and decimation stages progressively reduce the data rate while maintaining anti-aliasing protection.

Critical Concept: Decimation & Anti-Aliasing

All sampling systems must satisfy the Nyquist criterion (sampling rate ≥ 2× signal bandwidth). Engineering practice typically maintains a minimum ratio of about 2.5×, which the ADRV9009 meets across its configurations.

After R‑fold decimation, the maximum signal bandwidth the sampled data can carry reduces to (fs_original / (2R)). As the post‑decimation Nyquist frequency approaches the actual signal bandwidth, the decimation filter's transition band must become narrower—requiring higher filter orders. Consequently, later decimation stages employ higher‑order filters.

First Decimation Stage (DEC5 / Half‑Band 4× Decimation)

The first decimation factor is selected based on the signal bandwidth parameter: either 5× decimation or 4× decimation (two cascaded half‑band filters).

5× Decimation

• Because decimation by 5 cannot be implemented with a half‑band filter, a 33‑tap FIR filter is used.
• Direct 5× decimation requires strong anti‑aliasing; the 33‑tap filter provides the necessary attenuation.
• DEC5 is typically used for signal bandwidths between 100 MHz and 200 MHz (e.g., 150 MHz configurations).

% DEC5 filter coefficients (33 taps)
DEC5 = [0.002197, 0.004272, 0.006836, 0.008789, 0.008545, 0.003418, -0.004639, ...
        -0.015381, -0.025512, -0.029785, -0.022461, -0.002441, 0.03125, 0.074707, ...
        0.119141, 0.155396, 0.176758, 0.176758, 0.155396, 0.119141, 0.074707, ...
        0.03125, -0.002441, -0.022461, -0.029785, -0.025512, -0.015381, -0.004639, ...
        0.003418, 0.008545, 0.008789, 0.006836, 0.004272, 0.002197];

% freqz(DEC5); title('DEC5 Decimation Filter Response - 33 taps');

4× Decimation: Two‑Stage Half‑Band

• 4× decimation is implemented using two cascaded half‑band (HB) filters.
• First HB filter: 8 taps. Input sample rate is highest (1966.08 MHz). With I/Q baseband signal bandwidth of 50 MHz (100 MHz real), a lower‑order filter suffices.
• In this case, the first HB filter's passband extends to ~0.23 normalized frequency (~230 MHz), with 0.2 dB flatness from DC to 100 MHz.
• Anti‑aliasing explanation: For 2× decimation, frequencies in the 0.5–1.0 normalized band alias into 0–0.5. The HB filter provides >67 dB suppression from 0.77–1.0, effectively eliminating aliasing into the DC–0.23 region. Transition band content (0.23–0.77) is handled by subsequent filters.

% First half‑band filter (RHB3) - 8 taps
RHB3 = [-0.01874, -0.04218, 0.050476, 0.293884, 0.439636, 0.293884, 0.050476, -0.04218, -0.01874];
% freqz(RHB3); title('RHB3 Filter Response - 8 taps');

• Second HB filter: 18 taps. Input data rate is reduced to Fs/2. Signal bandwidth occupies DC–0.2 normalized (DC–50 MHz).
• Passband extends to 0.32 normalized; in‑band flatness within DC–0.2 is 0.004 dB.
• This filter suppresses components from 0.68–1.0, preventing aliasing into the DC–0.32 region, leaving a guard band (0.2–0.32).

% Second half‑band filter (RHB2) - 18 taps
RHB2 = [0.003174, 0, -0.01239, 0, 0.03418, 0, -0.08551, 0, 0.310913, 0.5, ...
        0.310913, 0, -0.08551, 0, 0.03418, 0, -0.01239, 0, 0.003174];
% freqz(RHB2); title('RHB2 Filter Response - 18 taps');

Second Decimation Stage (RHB1 Half‑Band Decimation)

• After the first decimation stage, the data rate is reduced to Fs/4 while signal bandwidth remains unchanged.
• To avoid aliasing, the second stage requires a higher‑order filter with steeper roll‑off.
• The ADRV9009 uses a 78‑tap half‑band filter (RHB1). Its transition band is extremely narrow (<0.1 normalized frequency), with stopband attenuation exceeding 70 dBc.
• For 200 MHz bandwidth configurations, this filter is bypassed.

% RHB1 filter - 78 taps (partial listing)
RHB1 = [-0.000122, 0, 0.000244, 0, -0.000488, 0, 0.000854, 0, -0.001221, 0, ...
        0.001831, 0, -0.002502, 0, 0.003479, 0, -0.004700, 0, 0.006287, 0, ...
        -0.008179, 0, 0.010620, 0, -0.013611, 0, 0.017578, 0, -0.022766, 0, ...
        0.030029, 0, -0.040955, 0, 0.059998, 0, -0.103027, 0, 0.313721, 0.493652, ...
        0.313721, 0, -0.103027, 0, 0.059998, 0, -0.040955, 0, 0.030029, 0, ...
        -0.022766, 0, 0.017578, 0, -0.013611, 0, 0.010620, 0, -0.008179, 0, ...
        0.006287, 0, -0.004700, 0, 0.003479, 0, -0.002502, 0, 0.001831, 0, ...
        -0.001221, 0, 0.000854, 0, -0.000488, 0, 0.000244, 0, -0.000122];
% freqz(RHB1); title('RHB1 Filter Response');

Third Decimation Stage (RFIR – Programmable FIR Filter)

• RFIR supports decimation by 1, 2, or 4, or can be bypassed.
• Used to compensate for the frequency response roll‑off of the analog TIA low‑pass filter.
• Configurable filter lengths: 24, 48, or 72 taps. Lower output data rates allow higher filter orders.
• Programmable gain options: +6 dB, 0 dB, −6 dB, or −12 dB.
• Maximum tap count is limited by the FIR clock rate (DPCLK, max 500 MHz). DPCLK = ADC clock rate ÷ 4 (when HB filters used) or ÷ 5 (when DEC5 used).
• Formula: Maximum filter taps = (DPCLK Clock Rate ÷ Receiver I/Q Data Rate) × 24
• In this case study: DPCLK = 245.76 MHz, Receiver I/Q data rate = 122.88 MHz → RFIR uses 48 taps.

Quick Start & Hardware Support

Ready to develop with ADRV9009? Explore this high‑performance SDR platform:

• YanTechLab ADRV9009 SDR Board (XC7Z100) – Preloaded firmware, ADI IIO Oscilloscope support, ideal for prototyping and evaluation.