ADRV9009 Development Environment Setup: From Cygwin to HDL Project Configuration

Complete ADRV9009 development environment setup on Windows. Covers Cygwin package selection, Vivado 2018.3 installation, HDL and no-OS repository cloning, make command troubleshooting, bitstream generation, and SDK project configuration.

If you've just received an ADRV9009 evaluation board and are staring at a pile of files, toolchains, and unfamiliar terminology, you may feel at a loss. When I first encountered this high-performance RF transceiver, it took me a full week to get the development environment in order. Online information is scattered, version dependencies are complex, and behind a seemingly simple make command may hide multiple environment configuration traps. This article is written for you — whether you're an RF system engineer, FPGA developer, or communication algorithm researcher, as long as you need to set up a complete ADRV9009 development flow in a Windows environment, you'll find a clear path and practical pitfall-avoidance experience here.

The ADRV9009, an agile transceiver supporting a 75 MHz to 6 GHz tuning range with bandwidth up to 200 MHz, involves a development environment that spans Hardware Description Language (HDL) projects, no-OS drivers, the Vivado/SDK toolchain, and the Cygwin simulation environment. The entire process is interlinked — any missed step can cause subsequent compilation failures. I'll use Vivado/SDK 2018.3 (currently the most stable and best-documented version combination) to walk you through setting up the environment from scratch, highlighting the easily overlooked pitfalls.

1. Basic Environment Preparation: Cygwin and Essential Toolchain

For FPGA-related projects on Windows, Cygwin is almost unavoidable. It provides a Unix-like environment that allows many Linux-based build scripts to run. But installing Cygwin isn't just clicking "Next" — especially for a project as sensitive to toolchain versions as ADRV9009.

1.1 Customized Cygwin Installation

First, download the installer from the Cygwin official website. On the "Choose Installation Type" page, be sure to select "Install from Internet", then choose a fast mirror site (e.g., Tsinghua or USTC mirrors). Next comes the critical step — package selection.

The default packages are far from sufficient. You need to manually add the following key packages:

• make: The core tool for building HDL projects, not installed by default. Search for "make" in the search box, find make: The GNU version of the 'make' utility under the "Devel" category, click "Skip" until a version number appears (e.g., 4.2.1), then click to select it.
• git: Used to clone ADI's official repositories from GitHub. Find git: Distributed version control system under the "Devel" category.
• curl and wget: Used for downloading files. Found under the "Web" category.
• perl: Some scripts depend on the Perl environment. Select perl: Perl interpreter under the "Perl" category.

For easy reference, here's a table of required packages:

After installation, add Cygwin's bin directory (e.g., C:\cygwin64\bin) to the system PATH environment variable. Then open Windows Command Prompt (CMD) or PowerShell and type make --version. If you see version information, the installation succeeded.

1.2 Vivado and SDK Version Locking

ADRV9009's HDL projects and no-OS drivers have strict requirements for Xilinx toolchain versions. In ADI's GitHub repository, different branches correspond to different Vivado versions. Based on my experience, the 2018_R2 branch typically corresponds to Vivado 2018.3 — a very stable combination.

• Download and install Vivado Design Suite 2018.3 from the Xilinx website. During installation, select the "Vivado HL WebPACK" version (free), but be sure to check the SDK component.
• After installation, remember to install the corresponding cable drivers for subsequent hardware debugging.
• Also add the Vivado and SDK launch script paths (e.g., C:\Xilinx\Vivado\2018.3\bin and C:\Xilinx\SDK\2018.3\bin) to the system PATH.

Version consistency is the cornerstone of avoiding strange errors later. I've seen people use Vivado 2020 to compile a 2018 project, only to get a pile of syntax errors during synthesis, wasting enormous amounts of time.

2. Obtaining Source Code: HDL Project and no-OS Drivers

ADI places hardware design (HDL) and software drivers (no-OS) in separate GitHub repositories. We need to obtain specific versions and ensure they match.

2.1 Clone and Switch the HDL Repository

Open Cygwin Terminal, choose a suitable directory (e.g., ~/projects), and execute:

git clone https://github.com/analogdevicesinc/hdl.git
cd hdl
git checkout hdl_2018_r2  # Switch to the branch corresponding to Vivado 2018.3

The hdl repository contains hardware design projects for all ADI FPGA boards. The project for ADRV9009 is located in the projects/adrv9009 directory. This project file (.xpr) is the core file we'll open in Vivado for synthesis, implementation, and bitstream generation.

2.2 Obtain Matching no-OS Drivers

The no-OS drivers are C programs running on the Zynq ARM processor, used to configure ADRV9009 registers and control data flow. In another terminal window or directory:

git clone https://github.com/analogdevicesinc/no-os.git
cd no-os
git checkout 2018_R1  # Note the branch name may differ slightly from HDL; 2018_R1 typically corresponds to 2018.3 SDK

3. Building the HDL Project: The Mysteries of Make and Troubleshooting

This is the most error-prone step in the entire process. We'll use the make command to automate Vivado project generation.

3.1 Execute the Make Command

Enter the projects/adrv9009 directory in the HDL repository, and you'll see several Makefile files. For the common ZC706/ADRV9009 evaluation board combination, execute:

cd hdl/projects/adrv9009/zc706
make

This make command performs a series of operations: downloading required IP core libraries (such as the adi-hdl library), running Tcl scripts to generate the Vivado project, adding source files, and configuring constraints. The entire process takes a long time — depending on network speed and computer performance, it may take 30 minutes to 1 hour.

3.2 Common Errors and Solutions

If all goes well, you'll eventually see a success message indicating the system_top.xpr file was generated. But in reality, you're more likely to encounter the following issues:

• Error 1: make: *** No rule to make target ... This usually means make can't find dependency files. First, check whether you're in the correct directory (zc706). Second, ensure network connectivity, because the script will attempt to download dependencies from GitHub. Sometimes GitHub access is unstable; try configuring a Git proxy or using a domestic mirror.
• Error 2: Tcl script execution error indicating missing IP cores or version mismatch This is often caused by version confusion. ADI's IP core library (adi-hdl) is referenced as a submodule. You need to ensure it's properly initialized and updated. In the hdl directory, try:

  git submodule init
  git submodule update

  If the problem persists, manually delete the ip folders under hdl/library and hdl/projects/adrv9009, then re-run make to force the script to re-download.
• Error 3: Vivado path error The Makefile may hard-code the Vivado installation path. If your installation path is different (e.g., not C:/Xilinx), you need to edit script files like hdl/projects/scripts/adi_make.tcl, or specify the path via the VIVADO_PATH environment variable. In Cygwin, set the environment variable first:

  export VIVADO_PATH=/cygdrive/c/Xilinx/Vivado/2018.3/bin/vivado.bat

  Note that Windows paths in Cygwin need to be converted to the /cygdrive/c/ format.

4. Generating the Bitstream in Vivado and Exporting Hardware

After the make command succeeds, you'll find the adrv9009_zc706.sdk folder and the system_top.xpr Vivado project file in the zc706 directory.

4.1 Synthesis, Implementation, and Bitstream Generation

Open system_top.xpr with Vivado 2018.3. After opening, in the left "Flow Navigator", click in sequence:

1. Run Synthesis
2. After synthesis succeeds, click Run Implementation
3. After implementation succeeds, click Generate Bitstream

Each step may take tens of minutes. During this process, you can check the "Messages" tab for warnings (Warning) or critical warnings (Critical Warning). Some timing warnings may appear during the first build — as long as there are no errors, you can typically continue. After successful generation, the bitstream file (.bit) will be located in the *.runs/impl_1 directory.

4.2 Exporting the Hardware Platform to SDK

This is a critical step connecting hardware and software. In Vivado, click File → Export → Export Hardware...

• In the dialog box that appears, be sure to check "Include bitstream".
• For the export path, select the default generated adrv9009_zc706.sdk folder. This will generate an .hdf (Hardware Description File) in that directory, containing the Zynq processor hardware configuration and bitstream.

5. Building and Debugging the no-OS Project in SDK

Open Xilinx SDK 2018.3. First, set the workspace to point to the hdl/projects/adrv9009/zc706 directory or a subdirectory.

5.1 Create a Hardware Platform Project

1. In SDK, click File → New → Board Support Package. Enter a project name (e.g., adrv9009_bsp) and click Next.
2. On the "Board Support Package Settings" page, select the hardware platform (hw_platform) — it will automatically recognize the .hdf file we just exported. Keep other settings as default and click Finish.

5.2 Import and Modify the no-OS Application Project

This is the most error-prone software configuration step.

1. Click File → New → Application Project.
2. Enter a project name (e.g., adrv9009_noos_app), select the adrv9009_bsp created in the previous step, and click Next.
3. On the "Templates" page, do not select any template — click Finish directly. This creates an empty project.
4. Now, import the previously cloned no-os driver code into this empty project. The simplest method: in SDK's "Project Explorer" view, right-click the newly created adrv9009_noos_app project, select Import... → File System. Then browse to the no-os repository directory.
5. Critical step: import files selectively. Do not import the entire no-os directory — only import specific subfolders related to ADRV9009. At minimum:
   • drivers/adrv9009/
   • drivers/api/ (some general APIs)
   • projects/adrv9009/zc706/ (project-specific source and linker scripts)
   • The necessary common header directory include/
6. After importing, you need to manually adjust the project's Include Paths and Symbols to ensure the compiler can find all header files. In the project Properties, find C/C++ Build → Settings:
   • In Tool Settings → ARM v7 gcc compiler → Directories, add all paths where .h files are located.
   • In Tool Settings → ARM v7 gcc compiler → Symbols, add necessary preprocessor macros such as XILINX, ZYNQ, etc. Specific macro definitions can be referenced from the existing Makefile in the no-os project.

5.3 Solving Compilation Errors

When compiling, you'll almost certainly encounter errors. The most common are "file not found" or "multiple definition".

• For missing header files: Carefully check the include paths, ensure they point to the correct locations, and use the correct relative path format. SDK is sometimes case-sensitive about paths.
• For duplicate definitions: This is usually because multiple versions of the same source file were accidentally imported, or files compiled for different platforms in the no-os driver were included simultaneously. You need to carefully check the "src" folder and remove or exclude from build those files that don't belong to the ZC706/ADRV9009 platform. For example, files related to Altera (Intel) FPGAs must be removed or excluded.

After some patient path adjustment and file filtering, when the project finally compiles successfully and generates the elf executable, congratulations — the most complex software environment setup is complete.

6. On-Board Debugging and Verification

Connect the ZC706 development board to your computer via JTAG (USB) and Ethernet. In SDK, configure the Hardware Server and download the bitstream (.bit file) and executable (.elf file) to the board's FPGA and ARM processor.

Through SDK's serial terminal (UART), you can see the startup messages printed by the no-OS program. If the program runs successfully and begins initializing the ADRV9009, you'll see relevant register read/write logs. At this point, you can use ADI's TALISE API functions to start configuring RF parameters such as center frequency, gain, and bandwidth.

7. Quick Project Validation

If you want to shorten development cycles and accelerate project validation, we recommend the following boards:

• XC7Z100 + ADRV9009 SDR with Preloaded Firmware
• XC7Z100 + AD9371 SDR with Preloaded Firmware