AMD Xilinx RFSoC Selection Guide: Gen 1/2/3 and DFE Families Explained

Complete selection guide for AMD Zynq UltraScale+ RFSoC families — Gen 1, Gen 2, Gen 3, and DFE. Compare RF-ADC/DAC channels, sample rates, logic resources, and target applications for 5G, radar, satellite communications, and DOCSIS 3.1.

As the only single-chip adaptive radio frequency platform, AMD's Zynq UltraScale+ RFSoC integrates RF-Analog and SD-FEC, providing hardware-adaptable solutions. It is widely used in 5G/LTE wireless technology, cable television DOCSIS 3.1, phased array radar, and satellite communications. The product portfolio covers Gen 1 through Gen 3 and DFE, featuring Direct-RF signal chains, programmable logic, and processing system capabilities.

I. Zynq UltraScale+ RFSoC Overview

Industry's Only Single-Chip Adaptive RF Platform

The Zynq UltraScale+ RFSoC integrates high-speed, high-precision ADCs and DACs with FPGA logic, allowing RF signals to be directly input into the FPGA device. This architecture significantly reduces PCB area, board-level communication latency, and product power consumption — a major advantage.

Integrated RF-Analog

Direct RF sampling data converters monolithically integrated on an adaptive SoC eliminate the need for external data converters. This delivers a highly flexible solution that reduces power consumption and space occupation by 50% compared to multi-component solutions, including elimination of high-power FPGA-to-analog interfaces such as JESD204. Additionally, this approach enables a highly flexible solution that shifts most RF signal processing to the digital domain.

SD-FEC

Zynq UltraScale+ RFSoC integrates a Soft Decision Forward Error Correction (SD-FEC) core IP block with Low-Density Parity-Check (LDPC) and turbo codec support. The hardened cores deliver over 1Gb/s performance with low latency, lower power consumption, and smaller footprint compared to soft logic implementations.

Hardened Digital Front End

The Zynq RFSoC DFE is the latest adaptive RFSoC platform, integrating hardened IP for critical DFE processing. Zynq RFSoC DFE delivers a highly flexible solution for 5G New Radio, capable of operating at input/output frequencies up to 7.125GHz with low power and low cost.

Hardware Adaptability

The Zynq UltraScale+ RFSoC architecture integrates FPGA fabric, providing flexibility to meet a wide range of requirements on the same base hardware. Manufacturers can use the same platform to address different requirements and emerging standards, enabling rapid response to new market opportunities.

Complete SoC for Single-Chip Radio

Zynq UltraScale+ RFSoC is a heterogeneous computing architecture that includes a complete Arm processing subsystem, FPGA fabric, and full analog-to-digital programmability in the RF signal chain. It not only provides a complete single-chip software-defined radio platform for different applications but also facilitates production of radio variants as market dynamics evolve.

II. Zynq UltraScale+ RFSoC Product Portfolio

Portfolio Scalability to Meet Current and Future Market Demands

III. Product Applications

5G and LTE Wireless Technology

With Zynq RFSoC, wireless infrastructure manufacturers can achieve unparalleled board area and power reduction, critical for massive MIMO deployment:

• Input/output operating frequencies up to 7.125GHz on a single device
• Device variants provide integrated LDPC SD-FEC cores and high DSP density for 5G baseband
• Optimal mmWave IF implementation, including fixed wireless access and mobile backhaul
• Hardened radio digital front end provides up to 400MHz bandwidth (8T8R) for 5G New Radio (Zynq RFSoC DFE only)

Remote PHY Support for Cable Access DOCSIS 3.1

Zynq UltraScale+ RFSoC helps cable access Multiple System Operators (MSOs) move PHY layer processing closer to homes through Remote PHY nodes, thereby increasing network capacity:

• RF-Analog supports strict power and packaging constraints
• LDPC compliant with DOCSIS 3.1 requirements
• Broader spectrum support for DOCSIS 4.0
• FPGA logic for future-proof full-duplex IP

Phased Array Radar / Digital Array Radar

As a single-chip TRX solution for scalable, multi-function, phased array radar, Zynq UltraScale+ RFSoC enables low-latency transmit and receive in early warning scenarios, achieving optimal response time:

• Full L-band sampling
• Partial S-band direct sampling, full S-band in second Nyquist zone
• Partial C-band direct sampling
• Hardware and software reconfigurable

Test and Measurement

Designers can leverage direct RF sampling, highly flexible, reconfigurable logic, and software programmability in Zynq UltraScale+ RFSoC to build high-speed, multi-function instruments for signal generation and signal analysis.

Satellite Communications

Designers can leverage direct RF sampling, highly flexible, reconfigurable logic, and software programmability in Zynq UltraScale+ RFSoC to build high-speed, multi-function instruments for signal generation and signal analysis in satellite communications.

IV. RFSoC Product Tables

1. Zynq UltraScale+ RFSoC Gen 1

Direct-RF Signal Chain Characteristics

Programmable Logic

Processing System Features (Common across ZU21DR–ZU29DR)

• APU: Quad-core Arm Cortex-A53 MPCore up to 1.33GHz
• RPU: Quad-core Arm Cortex-R5 MPCore up to 533MHz
• Memory: 256KB on-chip w/ECC; DDR4, DDR3, LPDDR4, Quad-SPI, NAND, eMMC
• High-speed connectivity: 4 PS-GTR, PCIe Gen1/2, SATA 3.1, DisplayPort 1.2a, USB 3.0, SGMII
• General connectivity: 214 PS I/O, UART, CAN, USB 2.0, I2C, SPI, 32b GPIO, RTC, WatchDog

2. Zynq UltraScale+ RFSoC Gen 2 (ZU39DR)

Direct-RF Signal Chain Characteristics

Programmable Logic (ZU39DR)

• System Logic Cells: 930K
• DSP Slices: 4,272
• Memory: 60.5 Mb
• GTY Transceivers: 16
• PCIe Gen 3x16: 2
• 100G Ethernet MAC/PCS w/ RS-FEC: 2
• Max I/O Pins: 408

3. Zynq UltraScale+ RFSoC Gen 3

Direct-RF Signal Chain Characteristics

Programmable Logic (Gen 3)

4. Zynq UltraScale+ RFSoC DFE

Direct-RF Signal Chain Characteristics

Programmable Logic (ZU65DR / ZU67DR)

• Logic Cells: 489K
• DSP Slices: 1,872
• Memory: 67.8 Mb
• GTY Transceivers: 8
• 100G Ethernet MAC/PCS w/ RS-FEC: 1
• Max I/O Pins: 152

Reference Hardware Platform

If you are exploring RFSoC-based designs, validating signal processing algorithms, or accelerating SDR, radar, or wireless communication projects, a professional RFSoC development platform can significantly shorten your development cycle.

For detailed specifications, technical documentation, and development resources:

👉 XCZU27DR RFSoC

👉Documentation

All product names, trademarks, and registered trademarks are the property of their respective owners. This guide is for educational and research purposes. Specifications are subject to change without notice.